Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Storage Class Memory with Computing Row Buffer: A Design Space Exploration., , , , , , , , , and . DATE, page 1-6. IEEE, (2021)Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities., , and . DATE, page 298-301. IEEE, (2020)Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces., , , , and . DATE, page 1634-1639. IEEE, (2018)Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs., , , , , , , , , and 10 other author(s). DATE, page 613-618. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures., , , , and . NANOARCH, page 7-12. ACM, (2016)High density emerging resistive memories: What are the limits?, , , , and . LASCAS, page 1-4. IEEE, (2017)Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro., , , , , , , , , and 9 other author(s). IMW, page 1-4. IEEE, (2023)Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution., , , , , , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (2): 40:1-40:26 (2022)27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking., , , , , , , , , and 12 other author(s). ISSCC, page 452-453. IEEE, (2014)Software platform dedicated for in-memory computing circuit evaluation., , , , and . RSP, page 43-49. ACM, (2017)