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4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging.

J. Kulkarni, C. Tokunaga, P. Aseron, T. Nguyen, C. Augustine, J. Tschanz, and V. De. ISSCC, page 1-3. IEEE, (2015)

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Giordano Paolo

Paolo Molteni

Paolo Bavaj

Paolo Fornara

Paolo Imperia

Other publications of authors with the same name

4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging.J. Kulkarni, C. Tokunaga, P. Aseron, T. Nguyen, C. Augustine, J. Tschanz, and V. De. ISSCC, page 1-3. IEEE, (2015)Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops.A. Raychowdhury, J. Tschanz, K. Bowman, S. Lu, P. Aseron, M. Khellah, B. Geuskens, C. Tokunaga, C. Wilkerson, T. Karnik and 1 other author(s). IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (3): 208-217 (2011)A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction.J. Xu, P. Hazucha, Z. Wu, P. Aseron, M. Huang, F. Paillet, G. Schrom, J. Tschanz, V. De, T. Karnik and 1 other author(s). IEEE J. Solid State Circuits, 43 (1): 61-68 (2008)Resilient microprocessor design for high performance & energy efficiency.K. Bowman, J. Tschanz, S. Lu, P. Aseron, M. Khellah, A. Raychowdhury, B. Geuskens, C. Tokunaga, C. Wilkerson, T. Karnik and 1 other author(s). ISLPED, page 355-356. ACM, (2010)Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor.S. Dighe, S. Vangal, P. Aseron, S. Kumar, T. Jacob, K. Bowman, J. Howard, J. Tschanz, V. Erraguntla, N. Borkar and 2 other author(s). IEEE J. Solid State Circuits, 46 (1): 184-193 (2011)A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance.J. Tschanz, K. Bowman, S. Lu, P. Aseron, M. Khellah, A. Raychowdhury, B. Geuskens, C. Tokunaga, C. Wilkerson, T. Karnik and 1 other author(s). ISSCC, page 282-283. IEEE, (2010)An IA-32 processor with a wide voltage operating range in 32nm CMOS.G. Ruhl, S. Dighe, S. Jain, S. Khare, S. Yada, V. Ambili, P. Salihundam, S. Ramani, S. Muthukumar, M. Srinivasan and 9 other author(s). Hot Chips Symposium, page 1-37. IEEE, (2012)An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS.S. Paul, V. Honkote, R. Kim, T. Majumder, P. Aseron, V. Grossnickle, R. Sankman, D. Mallik, S. Jain, S. Vangal and 2 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process.D. Somasekhar, Y. Ye, P. Aseron, S. Lu, M. Khellah, J. Howard, G. Ruhl, T. Karnik, S. Borkar, V. De and 1 other author(s). ISSCC, page 274-275. IEEE, (2008)Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor.S. Dighe, S. Vangal, P. Aseron, S. Kumar, T. Jacob, K. Bowman, J. Howard, J. Tschanz, V. Erraguntla, N. Borkar and 2 other author(s). ISSCC, page 174-175. IEEE, (2010)

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Disambiguation of "Aseron, Paolo A."