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A 5-Bit 500-MS/S Flash ADC using Time-Domain Comparison., , , , и . Journal of Circuits, Systems, and Computers, (2012)Low Power Cache with Successive Tag Comparison Algorithm., , , и . PATMOS, том 2799 из Lecture Notes in Computer Science, стр. 599-606. Springer, (2003)A New Energy x Delay-Aware Flip-Flop., , , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (6): 1552-1557 (2006)Survey and Analysis of Delay-Locked Loops Used in DRAM Interfaces., и . IEEE Trans. Very Large Scale Integr. Syst., 22 (4): 701-711 (2014)A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time., , , и . IEEE Trans. Very Large Scale Integr. Syst., 17 (10): 1461-1469 (2009)An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator., , , и . IEEE Trans. Very Large Scale Integr. Syst., 22 (10): 2156-2163 (2014)A 1-V 10-Gb/s/pin Single-Ended Transceiver With Controllable Active-Inductor-Based Driver and Adaptively Calibrated Cascaded-Equalizer for Post-LPDDR4 Interfaces., , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (1): 331-342 (2018)A Single-Inductor Eight-Channel Output DC-DC Converter With Time-Limited Power Distribution Control and Single Shared Hysteresis Comparator., , и . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (12): 3354-3367 (2013)A 1-mW Solar-Energy-Harvesting Circuit Using an Adaptive MPPT With a SAR and a Counter., , , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (6): 331-335 (2013)A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM., , и . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (10): 1207-1211 (2017)