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Disambiguation of "Miyano, Shinji"

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A 1.6 Gbyte/s data transfer rate 8 Mb embedded DRAM.

, , , , , , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 30 (11): 1281-1285 (November 1995)

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Shinji Koiwa

Shinji Maeda

 

Other publications of authors with the same name

A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energy., , , and . ISSCC, page 232-234. IEEE, (2012)An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications., , , , , , , , , and 3 other author(s). ISSCC, page 276-277. IEEE, (2008)0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme., , , , and . CICC, page 1-4. IEEE, (2011)A 65nm low-power embedded DRAM with extended data-retention sleep mode., , , , , , , , , and 1 other author(s). ISSCC, page 567-576. IEEE, (2006)A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme., , , , , , , , , and . ISLPED, page 85-90. ACM, (2012)A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges., , , , , , and . VLSIC, page 60-61. IEEE, (2012)Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress., , , and . IEICE Trans. Electron., 96-C (6): 759-765 (2013)13.4 A 7ns-access-time 25μW/MHz 128kb SRAM for low-power fast wake-up MCU in 65nm CMOS with 27fA/b retention current., , , , , , , , and . ISSCC, page 236-237. IEEE, (2014)A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction., , , , , , and . ISQED, page 489-492. IEEE, (2012)Near Threshold Voltage Word-Line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (8): 1635-1643 (2012)