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A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges.

, , , , , , и . VLSIC, стр. 60-61. IEEE, (2012)

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Shinichi Kotabe

 

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0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme., , , , и . ESSCIRC, стр. 354-357. IEEE, (2010)A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges., , , , , , и . VLSIC, стр. 60-61. IEEE, (2012)60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations., , , , , и . ESSCIRC, стр. 317-320. IEEE, (2012)Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) scheme., , , и . A-SSCC, стр. 165-168. IEEE, (2011)Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges., , , , , , и . IEEE J. Solid State Circuits, 48 (4): 924-931 (2013)0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme., , , , и . CICC, стр. 1-4. IEEE, (2011)A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme., , , , , , , , , и . ISLPED, стр. 85-90. ACM, (2012)