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Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents.

, , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1739-1748 (2016)

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Analysis of Bridging Defects in Sequential CMOS Circuits and their Current Testability., and . EDAC-ETC-EUROASIC, page 356-360. IEEE Computer Society, (1994)Bridging Defects Resistance Measurements in a CMOS Process., , and . ITC, page 892-899. IEEE Computer Society, (1992)Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs., and . DATE, page 490-494. IEEE Computer Society, (1998)Post-bond test of Through-Silicon Vias with open defects., , and . ETS, page 1-6. IEEE, (2014)Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents., , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1739-1748 (2016)Power-aware voltage tuning for STT-MRAM reliability., , , , , , and . ETS, page 1-6. IEEE, (2015)IDDQ testing: state of the art and future trends., , , , and . Integr., 26 (1-2): 167-196 (1998)RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST., , , , , and . ITC, page 814-823. IEEE Computer Society, (2002)Bridges in sequential CMOS circuits: current-voltage signatur., and . VTS, page 68-73. IEEE Computer Society, (1997)Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell., , , , , and . DATE, page 447-452. ACM, (2015)