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A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing.

, , , , , , , , and . ETS, page 153-158. IEEE Computer Society, (2011)

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Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption., , , , , , , and . J. Low Power Electron., 9 (2): 253-263 (2013)Innovative Techniques for Testing and Diagnosing SoCs.. Polytechnic University of Turin, Italy, (2015)Optimized embedded memory diagnosis., , , , , , , , and . DDECS, page 347-352. IEEE Computer Society, (2011)Peak Power Estimation: A Case Study on CPU Cores., , , , , , , and . Asian Test Symposium, page 167-172. IEEE Computer Society, (2012)Increasing fault coverage during functional test in the operational phase., , , , and . IOLTS, page 43-48. IEEE, (2013)An Enhanced Strategy for Functional Stress Pattern Generation for System-on-Chip Reliability Characterization., , , and . MTV, page 29-34. IEEE Computer Society, (2010)On-line software-based self-test of the Address Calculation Unit in RISC processors., , , , , , , and . ETS, page 1-6. IEEE Computer Society, (2012)A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing., , , , , , , , and . ETS, page 153-158. IEEE Computer Society, (2011)Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test., , , , and . J. Electron. Test., 30 (3): 317-328 (2014)Cumulative embedded memory failure bitmap display & analysis., , , , , , , and . DDECS, page 255-260. IEEE Computer Society, (2010)