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A process- and temperature- insensitive current-controlled delay generator for sampled-data systems.

H. Wei, U. Chio, Y. Zhu, S. Sin, S. U, and R. da Silva Martins. APCCAS, page 1192-1195. IEEE, (2008)

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Peter Seng

Stefan Seng

Katja Seng

Helmut Seng

Michael Seng

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A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations.Y. Zhu, C. Chan, S. U, and R. Martins. IEEE Trans. Very Large Scale Integr. Syst., 25 (1): 354-363 (2017)On the Design of a Programmable-Gain Amplifier With Built-In Compact DC-Offset Cancellers for Very Low-Voltage WLAN Systems.P. Mak, S. U., and R. Martins. IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (2): 496-509 (2008)A frequency up-conversion and two-step channel selection embedded CMOS D/A interface.K. Ieong, C. Fok, P. Mak, S. U., and R. Martins. ISCAS (1), page 392-395. IEEE, (2005)A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits.S. Sin, S. U., and R. Martins. ISCAS, IEEE, (2006)A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation.Y. Zhu, C. Chan, S. Sin, S. U., R. Martins, and F. Maloberti. IEEE J. Solid State Circuits, 47 (11): 2614-2626 (2012)A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS.L. Qiu, K. Tang, Y. Zheng, L. Siek, Y. Zhu, and S. U. IEEE Trans. Very Large Scale Integr. Syst., 26 (3): 572-583 (2018)An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H.S. Sin, L. Ding, Y. Zhu, H. Wei, C. Chan, U. Chio, S. U, R. Martins, and F. Maloberti. ESSCIRC, page 218-221. IEEE, (2010)A pseudo-differential comparator-based pipelined ADC with common mode feedforward technique.L. Ding, S. Chan, K. Wong, S. Sin, S. U, and R. da Silva Martins. APCCAS, page 276-279. IEEE, (2008)A robust NTF zero optimization technique for both low and high OSRs sigma-delta modulators.Y. Du, T. He, Y. Jiang, S. Sin, S. U, and R. Martins. APCCAS, page 29-32. IEEE, (2012)An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs.L. Ding, S. Sin, S. U., and R. Martins. APCCAS, page 208-211. IEEE, (2010)

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Disambiguation of "U, Seng-Pan"

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A process- and temperature- insensitive current-controlled delay generator for sampled-data systems.

Please choose a person to relate this publication to

Peter Seng

Stefan Seng

Katja Seng

Helmut Seng

Michael Seng

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "U, Seng-Pan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A process- and temperature- insensitive current-controlled delay generator for sampled-data systems.

Please choose a person to relate this publication to

Peter Seng

Stefan Seng

Katja Seng

Helmut Seng

Michael Seng

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A process- and temperature- insensitive current-controlled delay generator for sampled-data systems.