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Impact of Self-Heating in Wire Interconnection on Timing., , , , , , , , , and 2 other author(s). IEICE Trans. Electron., 93-C (3): 388-392 (2010)Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations., , , , , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (4): 990-997 (2009)Setup time, hold time and clock-to-Q delay computation under dynamic supply noise., and . CICC, page 1-4. IEEE, (2010)Proposal of Metrics for SSTA Accuracy Evaluation., , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (4): 808-814 (2007)A minimum decap allocation technique based on simultaneous switching for nanoscale SoC., and . CICC, page 21-24. IEEE, (2009)Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (10): 1948-1953 (2011)Gate delay estimation in STA under dynamic power supply noise., , , , and . ASP-DAC, page 775-780. IEEE, (2010)A Method to Derive SSO Design Rule Considering Jitter Constraint., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (4): 865-872 (2006)An Approach for Reducing Leakage Current Variation due to Manufacturing Variability., , , , , , , , , and 2 other author(s). IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (12): 3016-3023 (2009)