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Disambiguation of "Chatty, Kiran V."

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Implementation of diode and bipolar triggered SCRs for CDM robust ESD protection in 90 nm CMOS ASICs.

, , , , and . Microelectron. Reliab., 47 (7): 1030-1035 (2007)

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Mariam Kiran

Mudnakudu Nagaraju Kiran Kumar

Kiran Varanasi

Sedat Kiran

Aysha Kiran

 

Other publications of authors with the same name

Analysis of ESD failure mechanism in 65nm bulk CMOS ESD NMOSFETs with ESD implant., , , , , , , , and . Microelectron. Reliab., 46 (9-11): 1597-1602 (2006)Implementation of diode and bipolar triggered SCRs for CDM robust ESD protection in 90 nm CMOS ASICs., , , , and . Microelectron. Reliab., 47 (7): 1030-1035 (2007)Simulation of ESD protection devices in an advanced CMOS technology using a TCAD workbench based on an ESD calibration methodology., , , , , , and . Microelectron. Reliab., 50 (9-11): 1367-1372 (2010)Optical and Electrical Testing of Latchup in I/O Interface Circuits., , , , , , , and . ITC, page 236-245. IEEE Computer Society, (2003)Reliability aspects of gate oxide under ESD pulse stress., , , , , , , , , and 1 other author(s). Microelectron. Reliab., 49 (12): 1407-1416 (2009)Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology., , , , , , , , and . Microelectron. Reliab., 49 (12): 1417-1423 (2009)Latchup Analysis Using Emission Microscopy., , , , , , , , , and . Microelectron. Reliab., 43 (9-11): 1603-1608 (2003)Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICs., , , , , and . Microelectron. Reliab., 47 (7): 1069-1073 (2007)