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Disambiguation of "Kang, Seung-Hyuk"

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An Offset-Canceling Triple-Stage Sensing Circuit for Deep Submicrometer STT-RAM.

, , , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (7): 1620-1624 (2014)

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Jung-Hun Seung

Young-Hyuk Joo

Hyuk-Cheol Kwon

Woo-Hyuk Byun

Min-Hyuk Kim

 

Other publications of authors with the same name

STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (7): 1630-1634 (2014)Sensing margin trend with technology scaling in MRAM., , , , and . I. J. Circuit Theory and Applications, 39 (3): 313-325 (2011)A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (12): 1109-1113 (2015)High-performance low-power magnetic tunnel junction based non-volatile flip-flop., , , , , and . ISCAS, page 1953-1956. IEEE, (2014)Efficiency analysis of importance sampling in deep submicron STT-RAM design using uncontrollable industry-compatible model parameter., , , , and . ICECS, page 400-403. IEEE, (2015)CD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors., , , , , and . ICCAD, page 1-8. IEEE, (2013)Architecture design with STT-RAM: Opportunities and challenges., , , , , and . ASP-DAC, page 109-114. IEEE, (2016)Probabilistically Programmed STT-MRAM., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 2 (1): 42-51 (2012)Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach., , , , , and . IEEE Trans. Multi Scale Comput. Syst., 1 (4): 195-206 (2015)A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM)., , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (1): 181-186 (2012)