( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
MRAM Cell Technology for Over 500-MHz SoC.

, , , , , , , и . IEEE J. Solid State Circuits, 42 (4): 830-838 (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Hiroaki Kobayashi

Hiroaki Tanaka

 

Другие публикации лиц с тем же именем

1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times., , , , , , , , и . VLSIC, стр. 46-47. IEEE, (2012)A 90nm 12ns 32Mb 2T1MTJ MRAM., , , , , , , , , и 10 other автор(ы). ISSCC, стр. 462-463. IEEE, (2009)Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition., , , , , , , , , и 10 other автор(ы). IEEE J. Solid State Circuits, 56 (4): 1116-1128 (2021)High-speed simulator including accurate MTJ models for spintronics integrated circuit design., , , , , , , , , и 1 other автор(ы). ISCAS, стр. 1971-1974. IEEE, (2012)Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure., , , , , , , , , и 1 other автор(ы). VLSIC, стр. 172-. IEEE, (2015)A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications., , , , , , , , , и 6 other автор(ы). IEEE J. Solid State Circuits, 54 (11): 2991-3004 (2019)Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications., , , , , , , , , и 1 other автор(ы). IEICE Electron. Express, 10 (23): 20130772 (2013)10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications., , , , , , , , , и 4 other автор(ы). ISSCC, стр. 184-185. IEEE, (2014)Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage., , , , , , , , , и 10 other автор(ы). VLSI Circuits, стр. 1-2. IEEE, (2020)MRAM Cell Technology for Over 500-MHz SoC., , , , , , , и . IEEE J. Solid State Circuits, 42 (4): 830-838 (2007)