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Adaptive subthreshold timing-error detection 8 bit microcontroller in 65 nm CMOS.

, , , и . ISCAS, стр. 2953-2956. IEEE, (2012)

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Matthew Mellon

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A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS., , , , и . CICC, стр. 1-4. IEEE, (2014)Adaptive subthreshold timing-error detection 8 bit microcontroller in 65 nm CMOS., , , и . ISCAS, стр. 2953-2956. IEEE, (2012)A fully integrated self-oscillating switched-capacitor DC-DC converter for near-threshold loads., , , и . A-SSCC, стр. 1-4. IEEE, (2015)Fully integrated DC-DC converter and a 0.4V 32-bit CPU with timing-error prevention supplied from a prototype 1.55V Li-ion battery., , , , , , и . VLSIC, стр. 320-. IEEE, (2015)A 0.4-0.9V, 2.87pJ/cycle Near-Threshold ARM Cortex-M3 CPU with In-Situ Monitoring and Adaptive-Logic Scan., , , , , , , , , и 1 other автор(ы). COOL CHIPS, стр. 1-3. IEEE, (2020)Implementing Minimum-Energy-Point Systems With Adaptive Logic., , , и . IEEE Trans. Very Large Scale Integr. Syst., 24 (4): 1247-1256 (2016)Measurement of a system-adaptive error-detection sequential circuit with subthreshold SCL., , , и . NORCHIP, стр. 1-4. IEEE, (2011)Adaptive Sub-Threshold Test Circuit., , , , и . AHS, стр. 197-203. IEEE Computer Society, (2009)Rethinking DC-DC converter design constraints for adaptable systems that target the minimum-energy point., , , , и . ISLPED, стр. 383-388. IEEE, (2013)