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Disambiguation of "Ciampolini, Lorenzo"

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An Automated Design Methodology for Computational SRAM Dedicated to Highly Data-Centric Applications: Invited Paper.

, , , , , , , and . SLIP, page 4:1-4:7. ACM, (2022)

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Lorenzo Ciampolini

Lorenzo Cubillos

Lorenzo Sguaitamatti

Lorenzo Guiducci

Lorenzo Pettazzi

 

Other publications of authors with the same name

Multiple-pulse dynamic stability and failure analysis of low-voltage 6T-SRAM bitcells in 28nm UTBB-FDSOI., , , , , , , and . ISCAS, page 1452-1455. IEEE, (2013)Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI., , , , , , , , and . IEEE J. Solid State Circuits, 49 (7): 1499-1505 (2014)A Near-Instantaneous and Non-Invasive Erasure Design Technique to Protect Sensitive Data Stored in Secure SRAMs., , , , , , , , , and 1 other author(s). ESSCIRC, page 455-458. IEEE, (2021)28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications., , , , , , , , , and 11 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)Storage Class Memory with Computing Row Buffer: A Design Space Exploration., , , , , , , , , and . DATE, page 1-6. IEEE, (2021)A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI., , , , , and . ESSCIRC, page 429-432. IEEE, (2016)A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28-nm FD-SOI., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (4): 1257-1268 (2018)Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI., , , , , and . ESSCIRC, page 205-208. IEEE, (2013)Efficient yield estimation through generalized importance sampling with application to NBL-assisted SRAM bitcells., , , , , , , and . ICCAD, page 89. ACM, (2016)Impact of Random Telegraph Signals on 6T high-density SRAM in 28nm UTBB FD-SOI., , , , and . ESSDERC, page 94-97. IEEE, (2014)