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Disambiguation of "Giraud, Bastien"

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An Automated Design Methodology for Computational SRAM Dedicated to Highly Data-Centric Applications: Invited Paper.

, , , , , , , and . SLIP, page 4:1-4:7. ACM, (2022)

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Volker Giraud

Reinhard Giraud

Bastien Pietropaoli

Bastien Clausse

Xavier Giraud

 

Other publications of authors with the same name

Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities., , and . DATE, page 298-301. IEEE, (2020)Storage Class Memory with Computing Row Buffer: A Design Space Exploration., , , , , , , , , and . DATE, page 1-6. IEEE, (2021)Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro., , , , , , , , , and 9 other author(s). IMW, page 1-4. IEEE, (2023)Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces., , , , and . DATE, page 1634-1639. IEEE, (2018)Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs., , , , , , , , , and 10 other author(s). DATE, page 613-618. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures., , , , and . NANOARCH, page 7-12. ACM, (2016)High density emerging resistive memories: What are the limits?, , , , and . LASCAS, page 1-4. IEEE, (2017)SRAM Voltage and Current Sense Amplifiers in sub-32nm Double-gate CMOS Insensitive to Process Variations and Transistor Mismatch., , , , and . ISCAS, page 3170-3173. IEEE, (2009)Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology., , , , and . ICICDT, page 53-56. IEEE, (2013)A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS., , , , , , , , , and 3 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (9): 2438-2447 (2017)