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Improving security in cache memory by power efficient scrambling technique., , и . IET Comput. Digit. Tech., 9 (6): 283-292 (2015)On the Fitting and Improvement of RRAM Stanford-Based Model Parameters Using TiN/Ti/HfO2/W Experimental Data., , , , и . DCIS, стр. 1-6. IEEE, (2022)On High-Quality, Low Energy BIST Preparation at RT-Level., , , , , и . LATW, стр. 52-57. IEEE, (2002)Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results., , , и . PATMOS, том 2799 из Lecture Notes in Computer Science, стр. 80-89. Springer, (2003)Design and implementation of Automatic Test Equipment IP module., , , и . European Test Symposium, стр. 244. IEEE Computer Society, (2010)True Random Number Generator Based on the Variability of the High Resistance State of RRAMs., , , , , , , и . IEEE Access, (2023)RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST., , , , , и . ITC, стр. 814-823. IEEE Computer Society, (2002)Interleaved scrambling technique: A novel low-power security layer for cache memories., , и . ETS, стр. 1-2. IEEE, (2014)Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity., , , , , , , и . ISCAS (1), стр. 110-113. IEEE, (1999)Fault-Secure Parity Prediction Arithmetic Operators., , , и . IEEE Des. Test Comput., 14 (2): 60-71 (1997)