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Disambiguation of "Manich, Salvador"

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Low Power BIST by Filtering Non-Detecting Vectors.

, , , , , , , , , and . J. Electron. Test., 16 (3): 193-202 (2000)

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Michael Salvador

Salvador Herrador

Salvador Fernandes

Salvador Oberhaus

Salvador Millaleo

 

Other publications of authors with the same name

Improving security in cache memory by power efficient scrambling technique., , and . IET Comput. Digit. Tech., 9 (6): 283-292 (2015)On the Fitting and Improvement of RRAM Stanford-Based Model Parameters Using TiN/Ti/HfO2/W Experimental Data., , , , and . DCIS, page 1-6. IEEE, (2022)On High-Quality, Low Energy BIST Preparation at RT-Level., , , , , and . LATW, page 52-57. IEEE, (2002)Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results., , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 80-89. Springer, (2003)Design and implementation of Automatic Test Equipment IP module., , , and . European Test Symposium, page 244. IEEE Computer Society, (2010)True Random Number Generator Based on the Variability of the High Resistance State of RRAMs., , , , , , , and . IEEE Access, (2023)RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST., , , , , and . ITC, page 814-823. IEEE Computer Society, (2002)Interleaved scrambling technique: A novel low-power security layer for cache memories., , and . ETS, page 1-2. IEEE, (2014)A Highly Time Sensitive XOR Gate for Probe Attempt Detectors., and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (11): 786-790 (2013)Fault-Secure Parity Prediction Arithmetic Operators., , , and . IEEE Des. Test Comput., 14 (2): 60-71 (1997)