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Building Open Trusted Execution Environments.

, , , , и . IEEE Secur. Priv., 18 (5): 47-56 (2020)

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Optimizing Matrix Multiply Using PHiPAC: A Portable, High-Performance, ANSI C Coding Methodology., , , и . International Conference on Supercomputing, стр. 340-347. ACM, (1997)FASED: FPGA-Accelerated Simulation and Evaluation of DRAM., , , , , , и . FPGA, стр. 330-339. ACM, (2019)An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET., , , , , , , , , и 3 other автор(ы). IEEE J. Solid State Circuits, 57 (1): 140-152 (2022)Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors., , , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 23 (4): 723-730 (2015)Energy-aware lossless data compression., и . ACM Trans. Comput. Syst., 24 (3): 250-291 (2006)Building Open Trusted Execution Environments., , , , и . IEEE Secur. Priv., 18 (5): 47-56 (2020)The GAP Benchmark Suite., , и . CoRR, (2015)CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems., , , , , , , , , и 3 other автор(ы). ISCA, стр. 39:1-39:17. ACM, (2023)Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors., и . ISCA, стр. 336-345. IEEE Computer Society, (2005)A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET., , , , , , , , , и 9 other автор(ы). ESSCIRC, стр. 259-262. IEEE, (2021)