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Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.

K. Feng, T. Kong, K. Koul, J. Melchert, A. Carsello, Q. Liu, G. Nyengele, M. Strange, K. Zhang, A. Nayak, J. Setter, J. Thomas, K. Sreedhar, P. Chen, N. Bhagdikar, Z. Myers, B. D'Agostino, P. Joshi, S. Richardson, C. Torng, M. Horowitz, and P. Raina. IEEE J. Solid State Circuits, 59 (3): 947-959 (March 2024)

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Flavio Horowitz

Alexander Horowitz

Pinchas Horowitz

Wilhelm Horowitz

Other publications of authors with the same name

Towards an explanatory and computational theory of scientific discoveryC. Chen, Y. Chen, M. Horowitz, H. Hou, Z. Liu, and D. Pellegrino. CoRR, (2009)An Analytical Cache Model.A. Agarwal, M. Horowitz, and J. Hennessy. ACM Trans. Comput. Syst., 7 (2): 184-215 (1989)A high-speed, low-power 3D-SRAM architecture.H. Nho, M. Horowitz, and S. Wong. CICC, page 201-204. IEEE, (2008)A Verilog piecewise-linear analog behavior model for mixed-signal validation.S. Liao, and M. Horowitz. CICC, page 1-5. IEEE, (2013)Digital Analog Design: Enabling Mixed-Signal System Validation.B. Lim, J. Jang, J. Mao, J. Kim, and M. Horowitz. IEEE Des. Test, 32 (1): 44-52 (2015)A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs.K. Chang, J. Wei, C. Huang, S. Li, K. Donnelly, M. Horowitz, Y. Li, and S. Sidiropoulos. IEEE J. Solid State Circuits, 38 (5): 747-754 (2003)A 700-Mb/s/pin CMOS signaling interface using current integrating receivers.S. Sidiropoulos, and M. Horowitz. IEEE J. Solid State Circuits, 32 (5): 681-690 (1997)Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models.B. Lim, and M. Horowitz. IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (1): 23-33 (2016)A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs.A. Nayak, K. Zhang, R. Setaluri, A. Carsello, M. Mann, S. Richardson, R. Bahr, P. Hanrahan, M. Horowitz, and P. Raina. DATE, page 846-851. IEEE, (2020)CMOS Image Sensors With Multi-Bucket Pixels for Computational Photography.G. Wan, X. Li, G. Agranov, M. Levoy, and M. Horowitz. IEEE J. Solid State Circuits, 47 (4): 1031-1042 (2012)

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Disambiguation of "Horowitz, Mark"

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Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.

Please choose a person to relate this publication to

Flavio Horowitz

Alexander Horowitz

Pinchas Horowitz

Pinchas Horowitz

Wilhelm Horowitz

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Horowitz, Mark"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.

Please choose a person to relate this publication to

Flavio Horowitz

Alexander Horowitz

Pinchas Horowitz

Pinchas Horowitz

Wilhelm Horowitz

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.