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Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.

, , , , , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 59 (3): 947-959 (March 2024)

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Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 59 (3): 947-959 (March 2024)Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra., , , , , , , , , and 13 other author(s). VLSI Technology and Circuits, page 70-71. IEEE, (2022)Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators., , , , , , , and . ACM Trans. Archit. Code Optim., 20 (2): 26:1-26:26 (June 2023)AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers., , , , , , , , , and 23 other author(s). ACM Trans. Embed. Comput. Syst., 22 (2): 35:1-35:34 (March 2023)Automated Design Space Exploration of CGRA Processing Element Architectures using Frequent Subgraph Analysis., , , , , , , and . CoRR, (2021)Compiling Halide Programs to Push-Memory Accelerators., , , , , , , , , and 1 other author(s). CoRR, (2021)APEX: A Framework for Automated Processing Element Design Space Exploration using Frequent Subgraph Analysis., , , , , , , , and . ASPLOS (3), page 33-45. ACM, (2023)Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration., , , , , , , , , and 13 other author(s). HCS, page 1-30. IEEE, (2022)Creating an Agile Hardware Design Flow., , , , , , , , , and 22 other author(s). DAC, page 1-6. IEEE, (2020)