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Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.

K. Feng, T. Kong, K. Koul, J. Melchert, A. Carsello, Q. Liu, G. Nyengele, M. Strange, K. Zhang, A. Nayak, J. Setter, J. Thomas, K. Sreedhar, P. Chen, N. Bhagdikar, Z. Myers, B. D'Agostino, P. Joshi, S. Richardson, C. Torng, M. Horowitz, and P. Raina. IEEE J. Solid State Circuits, 59 (3): 947-959 (March 2024)

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Liu Liu

Keetsin Liu

Ching Liu

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Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators.X. Yang, M. Gao, Q. Liu, J. Setter, J. Pu, A. Nayak, S. Bell, K. Cao, H. Ha, P. Raina and 2 other author(s). ASPLOS, page 369-383. ACM, (2020)ASPLOS 2020 was canceled because of COVID-19..Compiling Halide Programs to Push-Memory Accelerators.Q. Liu, D. Huff, J. Setter, M. Strange, K. Feng, K. Sreedhar, Z. Wang, K. Zhang, M. Horowitz, P. Raina and 1 other author(s). CoRR, (2021)Low-overhead implementation of logic encryption using gate replacement techniques.X. Chen, Q. Liu, Y. Wang, Q. Xu, and H. Yang. ISQED, page 257-263. IEEE, (2017)Hardware Trojan Detection in Third-Party Digital Intellectual Property Cores by Multilevel Feature Analysis.X. Chen, Q. Liu, S. Yao, J. Wang, Q. Xu, Y. Wang, Y. Liu, and H. Yang. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (7): 1370-1383 (2018)AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers.K. Koul, J. Melchert, K. Sreedhar, L. Truong, G. Nyengele, K. Zhang, Q. Liu, J. Setter, P. Chen, Y. Mei and 23 other author(s). ACM Trans. Embed. Comput. Syst., 22 (2): 35:1-35:34 (March 2023)Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators.Q. Liu, J. Setter, D. Huff, M. Strange, K. Feng, M. Horowitz, P. Raina, and F. Kjolstad. ACM Trans. Archit. Code Optim., 20 (2): 26:1-26:26 (June 2023)FASTrust: Feature analysis for third-party IP trust verification.S. Yao, X. Chen, J. Zhang, Q. Liu, J. Wang, Q. Xu, Y. Wang, and H. Yang. ITC, page 1-10. IEEE, (2015)Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.K. Feng, T. Kong, K. Koul, J. Melchert, A. Carsello, Q. Liu, G. Nyengele, M. Strange, K. Zhang, A. Nayak and 12 other author(s). IEEE J. Solid State Circuits, 59 (3): 947-959 (March 2024)Automating System Configuration.N. Tsiskaridze, M. Strange, M. Mann, K. Sreedhar, Q. Liu, M. Horowitz, and C. Barrett. FMCAD, page 102-111. IEEE, (2021)Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.A. Carsello, K. Feng, T. Kong, K. Koul, Q. Liu, J. Melchert, G. Nyengele, M. Strange, K. Zhang, A. Nayak and 13 other author(s). VLSI Technology and Circuits, page 70-71. IEEE, (2022)

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Disambiguation of "Liu, Qiaoyi"

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Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.

Please choose a person to relate this publication to

Liu Liu

Liu Liu

Liu Liu

Keetsin Liu

Ching Liu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Liu, Qiaoyi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.

Please choose a person to relate this publication to

Liu Liu

Liu Liu

Liu Liu

Keetsin Liu

Ching Liu

Other publications of authors with the same name

Disambiguation

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URL
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Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.