( en | de | ru )

 

Disambiguation of "Nishimura, Kazuyoshi"

Author of the publication

copydeleteadd this publication to your clipboard
A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOS.

, , and . IEEE J. Solid State Circuits, 41 (9): 2052-2057 (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Kumi Nishimura

Masanobu Nishimura

Masanobu Nishimura

Tsuneko Nishimura

 

Other publications of authors with the same name

A 1ps-Resolution 2ns-Span 10Gb/s Data-Timing Generator with Spectrum Conversion., , , and . ISSCC, page 456-457. IEEE, (2008)Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit., , , , , and . ISSCC, page 104-105. IEEE, (2009)A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI., , , and . IEICE Trans. Electron., 91-C (4): 655-661 (2008)A 10Gb/s burst-mode adaptive gain select limiting amplifier in 0.13µm CMOS., , , , , and . ISSCC, page 940-949. IEEE, (2006)A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOS., , and . IEEE J. Solid State Circuits, 41 (9): 2052-2057 (2006)High sensitivity APD burst-mode receiver for 10Gbit/s TDM-PON system., , , , , , , , and . IEICE Electron. Express, 4 (19): 588-592 (2007)A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs., , , , , , , and . IEICE Trans. Electron., 91-C (6): 903-910 (2008)A 10.3125Gb/s Burst-Mode CDR Circuit using a δσ DAC., , , , , and . ISSCC, page 226-227. IEEE, (2008)