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Disambiguation of "Jung, Won-Young"

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A Digitally-Controlled SMPS Using a Novel High-Resolution DPWM Generator Based on a Pseudo Relaxation-Oscillation Technique.

, , , , and . IEICE Trans. Electron., 96-C (2): 277-284 (2013)

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Young Jung

Won-Young Hwang

Won-Young Choi

Suck-Young Won

Jung-Won Youn

 

Other publications of authors with the same name

A Latchup-Free ESD Power Clamp Circuit with Stacked-Bipolar Devices for High-Voltage Integrated Circuits., , , , , and . IEICE Trans. Electron., 92-C (5): 671-675 (2009)A Precision Floating-Gate Mismatch Measurement Technique for Analog Application., , , and . IEICE Trans. Electron., 94-C (5): 780-785 (2011)On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs., , , , , and . IEICE Trans. Electron., 93-C (5): 625-630 (2010)A Digitally-Controlled SMPS Using a Novel High-Resolution DPWM Generator Based on a Pseudo Relaxation-Oscillation Technique., , , , and . IEICE Trans. Electron., 96-C (2): 277-284 (2013)Fast and Accurate Power Bus Designer for Multi-Layers High-Speed Digital Boards., , and . IEICE Trans. Electron., 89-C (7): 1097-1105 (2006)A Novel High-Speed and Low-Voltage CMOS Level-Up/Down Shifter Design for Multiple-Power and Multiple-Clock Domain Chips., , , , and . IEICE Trans. Electron., 90-C (3): 644-648 (2007)Integrated interconnect circuit modeling for VLSI design., , , , and . ASP-DAC, ACM, (1995)Novel Method of Interconnect Worstcase Establishment with Statistically-Based Approaches., , , and . IEICE Transactions, 91-A (4): 1177-1184 (2008)A Non-snapback ESD Protection Clamp Circuit Using Isolated Parasitic Capacitance in a 0.35 µm Bipolar-CMOS-DMOS Process., , , , , and . IEICE Trans. Electron., 94-C (5): 796-801 (2011)