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Disambiguation of "Wee, Jae-Kyung"

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Fast and Accurate Power Bus Designer for Multi-Layers High-Speed Digital Boards.

, , and . IEICE Trans. Electron., 89-C (7): 1097-1105 (2006)

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Jae-Kyung Kim

Efren Wee

Choy Kyungcheol

Suk-Hun Kyung

Hong Wee

 

Other publications of authors with the same name

A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs., , , , , , , and . IEEE J. Solid State Circuits, 37 (2): 251-254 (2002)Current readout circuit using two-stage amplification method for 64-channel CNT arrays., , and . ISCAS, page 854-857. IEEE, (2012)A Digitally-Controlled SMPS Using a Novel High-Resolution DPWM Generator Based on a Pseudo Relaxation-Oscillation Technique., , , , and . IEICE Trans. Electron., 96-C (2): 277-284 (2013)An antifuse EPROM circuitry scheme for field-programmable repair in DRAM., , , , , , and . IEEE J. Solid State Circuits, 35 (10): 1408-1414 (2000)Low-voltage DRAM sensing scheme with offset-cancellation sense amplifier., , , and . IEEE J. Solid State Circuits, 37 (10): 1356-1360 (2002)One-chip multi-output SMPS using a shared digital controller and a pseudo relaxation oscillating technique., , , and . ISOCC, page 513-516. IEEE, (2012)Low power motion estimator architecture with leakage power reduction in deep sub-micron SoC., , , , and . Circuits, Signals, and Systems, page 85-89. IASTED/ACTA Press, (2004)Pipelined Bidirectional Bus Architecture for Embedded Multimedia SoCs., , , and . EUC, volume 3824 of Lecture Notes in Computer Science, page 350-359. Springer, (2005)Low-Power MPEG-4 Motion Estimator Design for Deep Sub-Micron Multimedia SoC., , , , and . KES (3), volume 3683 of Lecture Notes in Computer Science, page 449-455. Springer, (2005)A low-jitter wide-range skew-calibrated dual-loop DLL using antifuse circuitry for high-speed DRAM., , , , , , and . IEEE J. Solid State Circuits, 37 (6): 726-734 (2002)