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System-level PVT variation-aware power exploration of on-chip communication architectures.

, , , and . ACM Trans. Design Autom. Electr. Syst., 14 (2): 20:1-20:25 (2009)

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System-level PVT variation-aware power exploration of on-chip communication architectures., , , and . ACM Trans. Design Autom. Electr. Syst., 14 (2): 20:1-20:25 (2009)Model updating based on mixed-integer nonlinear programming under model-form uncertainty in finite element model., , , and . Eng. Comput., 37 (4): 3699-3725 (2021)Microarchitecture-Level SoC Design., , , , , and . Handbook of Hardware/Software Codesign, (2017)Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs., , , , , and . Asia-Pacific Computer Systems Architecture Conference, volume 4186 of Lecture Notes in Computer Science, page 295-308. Springer, (2006)Multiscale Structural Health Monitoring of Cable-Anchorage System Using Piezoelectric PZT Sensors., , and . IJDSN, (2013)System-level power-performance trade-offs in bus matrix communication architecture synthesis., , , and . CODES+ISSS, page 300-305. ACM, (2006)System-Level SRAM Yield Enhancement., , , , and . ISQED, page 179-184. IEEE Computer Society, (2006)Methodology for multi-granularity embedded processor power model generation for an ESL design flow., , , and . CODES+ISSS, page 255-260. ACM, (2008)System level power estimation methodology with H.264 decoder prediction IP case study., , , and . ICCD, page 601-608. IEEE, (2007)Ultra-low-power voice trigger for wearable devices., , , , , , , , and . ICCE-TW, page 76-77. IEEE, (2015)