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Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution.

, , , , , , and . DAC, page 71:1-71:6. ACM, (2017)

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A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture (Abstract Only)., , , , and . FPGA, page 270. ACM, (2015)An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS., , , , , , and . VLSI Circuits, page 37-38. IEEE, (2018)Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration., , , and . IEEE Trans. Parallel Distributed Syst., 29 (9): 2105-2120 (2018)Data-Flow Graph Mapping Optimization for CGRA With Deep Reinforcement Learning., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (12): 2271-2283 (2019)Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (12): 3081-3094 (2018)Massive MIMO Detection Algorithm and VLSI Architecture, , and . Springer, (2019)An efficient hardware design for cerebellar models using approximate circuits: special session paper., , and . CODES+ISSS, page 31:1-31:2. ACM, (2017)Reliability Evaluation of Phased-Mission Systems Using Stochastic Computation., , , and . IEEE Trans. Reliability, 65 (3): 1612-1623 (2016)Reconfigurable Architecture for Neural Approximation in Multimedia Computing., , , , and . IEEE Trans. Circuits Syst. Video Techn., 29 (3): 892-906 (2019)Constructing Concurrent Data Structures on FPGA with Channels., , , , and . FPGA, page 172-177. ACM, (2019)