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Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains.

L. Wang, X. Wen, S. Wu, H. Furukawa, H. Chao, B. Sheu, J. Guo, and W. Jone. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (2): 299-312 (2010)

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Hao-jan Tsai

Xiaofei Hao

Wenjin Hao

Yao Hao

Jin Hao

Other publications of authors with the same name

At-Speed Logic BIST for IP CoresB. Cheon, E. Lee, L. Wang, X. Wen, P. Hsu, J. Cho, J. Park, H. Chao, and S. Wu. CoRR, (2007)Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains.S. Wu, L. Wang, L. Yu, H. Furukawa, X. Wen, W. Jone, N. Touba, F. Zhao, J. Liu, H. Chao and 2 other author(s). DFT, page 358-366. IEEE Computer Society, (2010)Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains.L. Wang, X. Wen, S. Wu, H. Furukawa, H. Chao, B. Sheu, J. Guo, and W. Jone. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (2): 299-312 (2010)Physical-design-friendly hierarchical logic built-in self-test - A case study.K. Nelson, J. Shanmugavadivelu, J. Mekkoth, V. Ghanta, J. Wu, F. Zhuang, H. Chao, S. Wu, J. Rao, L. Yu and 1 other author(s). ISQED, page 1-6. IEEE, (2012)Practical Challenges in Logic BIST Implementation.S. Wu, H. Furukawa, B. Sheu, L. Wang, H. Chao, L. Yu, X. Wen, and M. Murakami. ATS, page 265. IEEE Computer Society, (2008)Turbo1500: Core-Based Design for Test and Diagnosis.L. Wang, R. Apte, S. Wu, B. Sheu, W. Jone, J. Guo, K. Lee, W. Wang, X. Wen, H. Chao and 5 other author(s). IEEE Des. Test Comput., 26 (1): 26-35 (2009)At-Speed Logic BIST for IP Cores.B. Cheon, E. Lee, L. Wang, X. Wen, P. Hsu, J. Cho, J. Park, H. Chao, and S. Wu. DATE, page 860-861. IEEE Computer Society, (2005)Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard.L. Wang, R. Apte, S. Wu, B. Sheu, K. Lee, X. Wen, W. Jone, C. Yeh, W. Wang, H. Chao and 6 other author(s). ITC, page 1-9. IEEE Computer Society, (2008)A circular pipeline processing based deterministic parallel test pattern generator.K. Yeh, J. Huang, H. Chao, and L. Wang. ITC, page 1-8. IEEE Computer Society, (2013)Logic BIST Architecture for System-Level Test and Diagnosis.J. Qian, X. Wang, Q. Yang, F. Zhuang, J. Jia, X. Li, Y. Zuo, J. Mekkoth, J. Liu, H. Chao and 5 other author(s). Asian Test Symposium, page 21-26. IEEE Computer Society, (2009)

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Disambiguation of "Chao, Hao-Jan"

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Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains.

Please choose a person to relate this publication to

Hao-jan Tsai

Xiaofei Hao

Wenjin Hao

Yao Hao

Jin Hao

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chao, Hao-Jan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains.

Please choose a person to relate this publication to

Hao-jan Tsai

Xiaofei Hao

Wenjin Hao

Yao Hao

Jin Hao

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains.