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Novel Double-Node-Upset-Tolerant Memory Cell Designs Through Radiation-Hardening-by-Design and Layout., , , , and . IEEE Trans. Reliability, 68 (1): 354-363 (2019)A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips., , , , and . IEEE Trans. Emerg. Top. Comput., 8 (3): 591-601 (2020)A dynamic test compaction procedure for high-quality path delay testing., , , , , and . ASP-DAC, page 348-353. IEEE, (2006)On estimation of NBTI-Induced delay degradation., , , , , and . European Test Symposium, page 107-111. IEEE Computer Society, (2010)A Static Method for Analyzing Hotspot Distribution on the LSI., , , , and . ITC-Asia, page 73-78. IEEE, (2019)A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (9): 1952-1956 (2021)Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node Upsets., , , , , , , and . IEEE Trans. Circuits Syst., 67-I (12): 4684-4695 (2020)A Study of Capture-Safe Test Generation Flow for At-Speed Testing., , , , , , , , , and 1 other author(s). IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (7): 1309-1318 (2010)A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing., , , , , , and . IEICE Trans. Inf. Syst., 96-D (9): 2003-2011 (2013)A Novel ATPG Method for Capture Power Reduction during Scan Testing., , , , , , and . IEICE Trans. Inf. Syst., 90-D (9): 1398-1405 (2007)