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A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed.

, , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 52 (10): 2769-2785 (2017)

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High Density Embedded 3D Stackable Via RRAM in Advanced MCU Applications., , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 52 (10): 2769-2785 (2017)A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 52 (8): 2194-2207 (2017)FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems., , , , , and . Integr., (2019)Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 50 (11): 2786-2795 (2015)7.4 A 256b-wordlength ReRAM-based TCAM with 1ns search-time and 14× improvement in wordlength-energyefficiency-density product using 2.5T1R cell., , , , , , , , , and 1 other author(s). ISSCC, page 136-137. IEEE, (2016)4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic., , , , , , , , , and 5 other author(s). ISSCC, page 84-86. IEEE, (2016)