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A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 52 (1): 250-260 (2017)A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 43 (11): 2381-2389 (2008)22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme., , , , , , , , , and 25 other author(s). ISSCC, page 330-332. IEEE, (2020)18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution., , , , , , , , , and 11 other author(s). ISSCC, page 316-317. IEEE, (2016)A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme., , , , , , , , , and 16 other author(s). IEEE J. Solid State Circuits, 56 (1): 199-211 (2021)A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus., , , , , , , , , and 24 other author(s). ISSCC, page 446-448. IEEE, (2022)A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ., , , , , , , , , and 24 other author(s). IEEE J. Solid State Circuits, 58 (1): 279-290 (2023)A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 47 (1): 107-116 (2012)A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking., , , , , , , , , and 13 other author(s). ISSCC, page 496-498. IEEE, (2011)