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Disambiguation of "Chu, Yuan-Hua"

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MORAS: An energy-scalable system using adaptive voltage scaling.

, , , , and . VLSI-DAT, page 1-4. IEEE, (2018)

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Hua Yuan

Chi-Hua Chu

Chia-hua Chu

Xiugan Yuan

Li Yuan

 

Other publications of authors with the same name

Collaborative voltage scaling with online STA and variable-latency datapath., , , , , , , and . ACM Great Lakes Symposium on VLSI, page 347-352. ACM, (2010)Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (12): 947-951 (2014)PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems., , , , , and . SoCC, page 136-139. IEEE, (2014)Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits., , , , , and . ISCAS, page 1572-1575. IEEE, (1995)A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation range., , , , , , and . SoCC, page 92-97. IEEE, (2013)A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 48 (10): 2558-2569 (2013)A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme., , , , , , , , , and . IEEE J. Solid State Circuits, 46 (4): 815-827 (2011)A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques., , , , , , , , , and 2 other author(s). VLSIC, page 112-113. IEEE, (2012)A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS., , , , , , and . A-SSCC, page 361-364. IEEE, (2014)Design of STR level converters for SoCs using the multi-island dual-VDD design technique., , , and . ISCAS, IEEE, (2006)