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Delay Constrained Register Transfer Level Dynamic Power Estimation.

, , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 36-46. Springer, (2006)

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FERRARI: A Tool for The Validation of System Dependability Properties., , and . FTCS, page 336-344. IEEE Computer Society, (1992)Hierarchical design and analysis of fault-tolerant multiprocessor systems using concurrent error detection., and . FTCS, page 130-137. IEEE Computer Society, (1990)Non-speculative double-sampling technique to increase energy-efficiency in a high-performance processor., , and . DATE, page 254-257. EDA Consortium San Jose, CA, USA / ACM DL, (2013)System accuracy estimation of SRAM-based device authentication., , and . ASP-DAC, page 37-42. IEEE, (2011)Real-time checking of linear control systems using analog checksums., , , and . IOLTS, page 122-127. IEEE, (2013)ESIFT: Efficient System for Error Injection., , and . IOLTS, page 201-206. IEEE, (2018)A Framework for Distributed VLSI Simulation on a Network of Workstations., and . Simulation, 60 (2): 95-104 (1993)On efficient generation of instruction sequences to test for delay defects in a processor., , , and . ACM Great Lakes Symposium on VLSI, page 279-284. ACM, (2008)Quantitative evaluation of soft error injection techniques for robust system design., , , , and . DAC, page 101:1-101:10. ACM, (2013)Delay Constrained Register Transfer Level Dynamic Power Estimation., , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 36-46. Springer, (2006)