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A Resonant Global Clock Distribution for the Cell Broadband Engine Processor., , , , , , , , , and . IEEE J. Solid State Circuits, 44 (1): 64-72 (2009)Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor., , , , , , , , , and 13 other author(s). ASP-DAC, page 871-878. IEEE, (2006)The design methodology and implementation of a first-generation CELL processor: a multi-core SoC., , , , , , , , , and 8 other author(s). CICC, page 45-49. IEEE, (2005)A Resonant Global Clock Distribution for the Cell Broadband-Engine Processor., , , , , , , , , and . ISSCC, page 512-513. IEEE, (2008)Implementation of the 65nm Cell Broadband Engine., , , , , , , , , and 4 other author(s). CICC, page 717-720. IEEE, (2007)The circuit and physical design of the POWER4 microprocessor., , , , , , , , and . IBM J. Res. Dev., 46 (1): 27-52 (2002)Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor., , , , , , , , , and 14 other author(s). IEEE J. Solid State Circuits, 41 (1): 179-196 (2006)