( en | de | ru )

 

Disambiguation of "Bellido, Manuel J."

Author of the publication

copydeleteadd this publication to your clipboard
Static Power Consumption in CMOS Gates Using Independent Bodies.

, , , , , , and . PATMOS, volume 4644 of Lecture Notes in Computer Science, page 404-412. Springer, (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Manuel J A Eugster

Manuel J A Eugster

Manuel J A Eugster

Manuel

Norbert J J Bock

 

Other publications of authors with the same name

Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates., , , , , and . PATMOS, volume 5349 of Lecture Notes in Computer Science, page 389-398. Springer, (2008)Multimedia System for Instruction and Learning Electronics., , , and . CALISCE, volume 1108 of Lecture Notes in Computer Science, page 442-444. Springer, (1996)New CMOS VLSI linear self-timed architectures., , , , , and . ASYNC, page 14-23. IEEE Computer Society, (1995)Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements., , , , , , and . IES, page 1-7. IEEE, (2006)Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits., , , , and . PATMOS, volume 1918 of Lecture Notes in Computer Science, page 316-326. Springer, (2000)SODS: a new CMOS differential-type structure., , , , and . IEEE J. Solid State Circuits, 30 (7): 835-838 (July 1995)Inertial and degradation delay model for CMOS logic gates., , , , and . ISCAS, page 459-462. IEEE, (2000)Degradation Delay Model Extension to CMOS Gates., , , , and . PATMOS, volume 1918 of Lecture Notes in Computer Science, page 149-158. Springer, (2000)Internode: Internal Node Logic Computational Model., , , , , and . Annual Simulation Symposium, page 241-248. IEEE Computer Society, (2003)HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model., , , , and . DATE, page 467-471. IEEE Computer Society, (2001)