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Disambiguation of "Matsui, Masataka"

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A 110-MHz/1-Mb synchronous TagRAM.

, , , , , , , , , , , and . IEEE J. Solid State Circuits, 29 (4): 403-410 (April 1994)

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Masataka Ohno

Takaoki Matsui

Masataka Miyawaki

Torao Matsui

Uwe Matsui

 

Other publications of authors with the same name

Energy-efficient 32 × 32-bit multiplier in tunable near-zero threshold CMOS., , and . ISLPED, page 268-272. ACM, (2000)Visconti: multi-VLIW image recognition processor based on configurable processor obstacle detection applications., , , , , , , , , and . CICC, page 185-188. IEEE, (2003)Development of Image Recognition Processor Based on Configurable Processor., , , , , , , , and . J. Robotics Mechatronics, 17 (4): 437-446 (2005)Design Methodology and System for a Configurable Media Embedded Processor Extensible to VLIW Architecture., , , , , , , , and . ICCD, page 2-7. IEEE Computer Society, (2002)Complexity Based Fast Coding Mode Decision for MPEG-2 / H.264 Video Transcoding., , , , , and . APCCAS, page 574-577. IEEE, (2006)A single-chip MPEG-2 codec based on customizable media microprocessor., , , , , , , , , and 5 other author(s). CICC, page 163-166. IEEE, (2002)DSP for wireless., and . CICC, page 66-67. IEEE, (2005)A 200 MHz 13 mm2 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme., , , , , , , , and . IEEE J. Solid State Circuits, 29 (12): 1482-1490 (December 1994)A single-chip MPEG-2 codec based on customizable media embedded processor., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 38 (3): 530-540 (2003)Content-Based Complexity Reduction Methods for MPEG-2 to H.264 Transcoding., , , , , and . IEICE Trans. Inf. Syst., 90-D (1): 90-98 (2007)