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Design of Asynchronous Controllers with Delay Insensitive Interface., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A (12): 2577-2585 (2002)Analysis of Petri Nets by Ordering Relations in Reduced Unfoldings., , , and . Formal Methods Syst. Des., 12 (1): 5-38 (1998)Quasi-static Scheduling for Concurrent Architectures., , , , and . Fundam. Informaticae, 62 (2): 171-196 (2004)A region-based theory for state assignment in speed-independent circuits., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (8): 793-812 (1997)Coupling Asynchrony and Interrupts: Place Chart Nets., , , , , and . ICATPN, volume 1248 of Lecture Notes in Computer Science, page 328-347. Springer, (1997)Incremental high-level synthesis., , , , , , and . ASP-DAC, page 701-706. IEEE, (2010)Checking signal transition graph implementability by symbolic BDD traversal., , , , , and . ED&TC, page 325-332. IEEE Computer Society, (1995)Synthesis methodology for built-in at-speed testing., , and . ICCAD, page 183-188. IEEE Computer Society, (2005)Realistic performance-constrained pipelining in high-level synthesis., , , and . DATE, page 1382-1387. IEEE, (2011)Exploiting area/delay tradeoffs in high-level synthesis., , , and . DATE, page 1024-1029. IEEE, (2012)