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An efficient algorithm for custom instruction enumeration., and . ACM Great Lakes Symposium on VLSI, page 187-192. ACM, (2011)A formal method for hardware IP design and integration under I/O and timing constraints., , , , and . ACM Trans. Embed. Comput. Syst., 5 (1): 29-53 (2006)Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis., , and . IEEE Trans. Very Large Scale Integr. Syst., 16 (11): 1454-1464 (2008)An algorithm with improved delay for enumerating connected induced subgraphs of a large cardinality., , and . CoRR, (2021)Algorithms with improved delay for enumerating connected induced subgraphs of a large cardinality., , and . Inf. Process. Lett., (January 2024)Energy-Aware Partial-Duplication Task Mapping Under Real-Time and Reliability Constraints., , , and . SAMOS, volume 12471 of Lecture Notes in Computer Science, page 213-227. Springer, (2020)Architectural Synthesis with Interconnection Cost Control., , and . VLSI, volume 162 of IFIP Conference Proceedings, page 509-520. Kluwer, (1999)Synthèse architecturale d'applications temps réel pour technologies submicroniques., , and . Technique et Science Informatiques, 23 (1): 35-66 (2004)High-level synthesis for the design of FPGA-based signal processing systems., and . ICSAMOS, page 25-32. IEEE, (2009)Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems., , and . Signal Process., 86 (7): 1375-1399 (2006)