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A Priori Implementation Effort Estimation for Hardware Design Based on Independent Path Analysis., , , , , and . EURASIP J. Embed. Syst., (2008)Synchronization Processor Synthesis for Latency Insensitive Systems., , and . DATE, page 896-897. IEEE Computer Society, (2005)C-based rapid prototyping for digital signal processing., , , , , and . EUSIPCO, page 1-4. IEEE, (2005)Orcc's compa-backend demonstration., , , , , , , , and . DASIP, page 1-2. IEEE, (2014)Networked Self-adaptive Systems: An Opportunity for Configuring in the Large., , , , , , , and . ERSA, page 81-90. CSREA Press, (2009)A Networked, Lightweight and Partially Reconfigurable Platform., , and . ARC, volume 4943 of Lecture Notes in Computer Science, page 314-319. Springer, (2008)Virtual UARTs for Reconfigurable Multi-processor Architectures., , and . IPDPS Workshops, page 252-259. IEEE, (2013)Hardware Virtual Components Compliant with Communication System Standards., , , , , , , and . DSD, page 88-95. IEEE Computer Society, (2005)Application-aware Multi-Objective Routing based on Genetic Algorithm for 2D Network-on-Chip., , and . Microprocess. Microsystems, (2018)Synchronization Processor Synthesis for Latency Insensitive Systems, , and . CoRR, (2007)