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Disambiguation of "Poon, Chi Fung"

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A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET.

, , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 54 (1): 18-28 (2019)

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Bruce Poon

Siuwah Fung

Pat Fung

Reginald Fung

Michael Fung

 

Other publications of authors with the same name

A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS., , , , , , , , , and 6 other author(s). VLSIC, page 104-105. IEEE, (2012)A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 54 (1): 18-28 (2019)A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET., , , , , , , , , and 5 other author(s). VLSI Circuits, page 47-48. IEEE, (2018)A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET., , , , , , , , , and 6 other author(s). ISSCC, page 108-110. IEEE, (2018)A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 57 (4): 1199-1210 (2022)A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET., , , , , , , , , and 3 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)