Author of the publication

A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET.

, , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 54 (1): 18-28 (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A 0.5-16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 52 (7): 1783-1797 (2017)A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS., , , , , , , , , and 6 other author(s). VLSIC, page 104-105. IEEE, (2012)3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS., , , , , , , , , and 6 other author(s). ISSCC, page 1-3. IEEE, (2015)Classifying Approximation Algorithms: Understanding the APX Complexity Class., and . CoRR, (2021)A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 54 (1): 18-28 (2019)A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET., , , , , , , , , and 6 other author(s). ISSCC, page 108-110. IEEE, (2018)A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET., , , , , , , , , and 7 other author(s). ESSCIRC, page 297-300. IEEE, (2016)A 2.25pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET., , , , , , , , , and 9 other author(s). CICC, page 1-8. IEEE, (2019)Typhoon: Towards an Effective Task-Specific Masking Strategy for Pre-trained Language Models., , and . CoRR, (2023)Matching Markets., , and . CoRR, (2021)