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Disambiguation of "Park, Kwang-Il"

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Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond.

, , , , , , , , , , , , , , , , , , , and . HCS, page 1-26. IEEE, (2021)

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Kwang Park

Sun-Kwang Park

Kwang Woo Park

Kwang-jack Park

Kwang-Ki Park

 

Other publications of authors with the same name

A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration., , , , , , , , , and 14 other author(s). VLSI Circuits, page 114-. IEEE, (2019)HMM and Rule-Based Hybrid Intruder Detection Approach by Synthesizing Decisions of Sensors., , , , , and . Int. J. Distributed Sens. Networks, (2013)A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces., , , , and . IEEE J. Solid State Circuits, 44 (5): 1522-1530 (2009)23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme., , , , , , , , , and 27 other author(s). ISSCC, page 390-391. IEEE, (2017)Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices., , , , , , , , , and 2 other author(s). HPCA, page 61-72. IEEE Computer Society, (2017)A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW., , , , , , , , , and 19 other author(s). ISSCC, page 498-500. IEEE, (2011)A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking., , , , , , , , , and 39 other author(s). ISSCC, page 204-206. IEEE, (2018)A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power., , , , , , , , , and 20 other author(s). ISSCC, page 378-380. IEEE, (2019)A Bandwidth-Efficient Implementation of Mesh with Multiple Broadcasting., , , and . ICPP, page 434-443. IEEE Computer Society, (1999)A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process., , , , , , , , , and 37 other author(s). ISSCC, page 206-208. IEEE, (2018)