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A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications., , , , , , and . Integr., (2022)Valid test pattern identification for VLSI adaptive test., , , and . Integr., (2022)A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications., , , , , , and . IEEE Trans. Aerosp. Electron. Syst., 56 (4): 2666-2676 (2020)A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells., , , , , , , , and . ITC-Asia, page 139-144. IEEE, (2019)Design of Wireless Network on Chip with Priority-Based MAC., , , , , and . Journal of Circuits, Systems, and Computers, 28 (8): 1950124:1-1950124:18 (2019)Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS., , , , and . Microelectron. J., (2017)Method of generating strategic guidance information for driving evacuation flows to approach safety-based system optimal dynamic flows: Case study of a large stadium., , , , and . J. Systems Science & Complexity, 28 (3): 606-622 (2015)A high performance SEU-tolerant latch for nanoscale CMOS technology.. DATE, page 1-5. European Design and Automation Association, (2014)Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications., , , , , , , , and . IEEE Trans. Aerosp. Electron. Syst., 58 (1): 517-529 (2022)Jitter-Quantizing-Based TRNG Robust Against PVT Variations., , , , , , , and . IEEE Access, (2020)