Novelics, a leading provider of system-on-chip (SoC) embedded memory intellectual property (IP), announced the availability of its one-transistor SRAM for 65-nanometer semiconductor design, the only SRAM-1T memory available to SoC designers in bulk CMOS using the standard silicon wafer process. Novelics’ coolSRAM-1T is designed to optimize memory-intensive applications in computing, networking, wireless, multimedia, graphics, automotive, consumer electronics products and more by:
* Shrinking the SoC embedded memory area up to 50 percent versus using industry-standard SRAM
* Lowering development time and costs through standard bulk CMOS that eliminates extra mask layers and special processing steps
* Reducing memory leakage power consumption by a factor of 10
* Offering the opportunity in many designs to reduce or eliminate off-chip memory systems, enabling dramatic savings in system cost and power consumption
ReSP is an MPSoC simulation platform working at a high abstraction level; components used by ReSP are based on SystemC and TLM hardware and communication description libraries. ReSP provides a non-intrusive framework to manipulate SystemC and TLM objects. The simulation platform is built using Python programming language; its reflective capabilities augment the platform with the possibility of observing the internal structure of the SystemC component models. This feature enables run-time composition and dynamic management of the architecture under analysis. The full potentialities offered by the integration among Python and SystemC are exploited, during simulation, to query, examine and, possibly, modify the internal status of the hardware models. These capabilities simplify the debugging process for both the modeled hardware architecture and the software running on it.
M. Ekstrand, M. Ludwig, J. Konstan, und J. Riedl. Proceedings of the Fifth ACM Conference on Recommender Systems, Seite 133--140. New York, NY, USA, ACM, (2011)