%0 Conference Paper %1 conf/vlsic/UpadhyayaBMZICT16 %A Upadhyaya, Parag %A Bekele, Ade %A Melek, Didem Turkur %A Zhao, Haibing %A Im, Jay %A Cho, Junho %A Tan, Kee Hian %A McLeod, Scott %A Chen, Stanley %A Zhang, Wenfeng %A Frans, Yohan %A Chang, Ken %B VLSI Circuits %D 2016 %I IEEE %K dblp %P 1-2 %T A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#UpadhyayaBMZICT16 %@ 978-1-5090-0635-9

@inproceedings{conf/vlsic/UpadhyayaBMZICT16, added-at = {2016-09-26T00:00:00.000+0200}, author = {Upadhyaya, Parag and Bekele, Ade and Melek, Didem Turkur and Zhao, Haibing and Im, Jay and Cho, Junho and Tan, Kee Hian and McLeod, Scott and Chen, Stanley and Zhang, Wenfeng and Frans, Yohan and Chang, Ken}, biburl = {https://www.bibsonomy.org/bibtex/23a6783faa1db8390b9a7c07e589d3e28/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2016}, ee = {http://dx.doi.org/10.1109/VLSIC.2016.7573471}, interhash = {00057cad1bef9422775a41d71c194c71}, intrahash = {3a6783faa1db8390b9a7c07e589d3e28}, isbn = {978-1-5090-0635-9}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2016-09-27T11:36:21.000+0200}, title = {A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#UpadhyayaBMZICT16}, year = 2016 }