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Disambiguation of "Chen, Stanley"

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A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology.

, , , , , , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)

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Dolores Stanley

Stanley Baksi

Stanley Heinze

Stanley Durrleman

Stanley Tang

 

Other publications of authors with the same name

A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS., , , , , , , , , and 6 other author(s). VLSIC, page 104-105. IEEE, (2012)3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS., , , , , , , , , and 6 other author(s). ISSCC, page 1-3. IEEE, (2015)PC-CUBE, a personal computer based hypercube., , , , , , , and . C³P, page 92-97. ACM, (1988)A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology., , , , , , , , , and 2 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET., , , , , , , , , and 7 other author(s). ISSCC, page 114-115. IEEE, (2017)A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET., , , , , , , , , and . ISSCC, page 390-392. IEEE, (2018)2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS., , , , , , , and . ISSCC, page 52-53. IEEE, (2014)A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET., , , , , , , , , and 7 other author(s). VLSI Circuits, page 145-146. IEEE, (2018)6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET., , , , , , , , , and 11 other author(s). ISSCC, page 116-118. IEEE, (2020)Normalization of non-standard words., , , , , and . Computer Speech & Language, 15 (3): 287-333 (2001)