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3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS., , , , , , , , , и 6 other автор(ы). ISSCC, стр. 1-3. IEEE, (2015)A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 204-205. IEEE, (2023)A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET., , , , , , , , , и 7 other автор(ы). VLSI Circuits, стр. 145-146. IEEE, (2018)A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET., , , , , , , , , и 7 other автор(ы). ESSCIRC, стр. 297-300. IEEE, (2016)A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET., , , , , , , , , и 4 other автор(ы). VLSI Circuits, стр. 1-2. IEEE, (2016)6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET., , , , , , , , , и 11 other автор(ы). ISSCC, стр. 116-118. IEEE, (2020)Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS., , , , , , , , , и 3 other автор(ы). CICC, стр. 1-4. IEEE, (2014)Design of high-speed wireline transceivers for backplane communications in 28nm CMOS., , , , , , , , , и 1 other автор(ы). CICC, стр. 1-4. IEEE, (2012)A 32.75-Gb/s voltage mode transmitter with 3-tap FFE in 16nm CMOS., , , , , , , , , и 1 other автор(ы). A-SSCC, стр. 233-236. IEEE, (2016)A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology., , , , , , , , , и 2 other автор(ы). VLSI Circuits, стр. 1-2. IEEE, (2016)