Please log in to take part in the discussion (add own reviews or comments).
Cite this publication
More citation styles
- please select -
%0 Journal Article
%1 journals/jssc/MansuriJKHSBORMC13
%A Mansuri, Mozhgan
%A Jaussi, James E.
%A Kennedy, Joseph T.
%A Hsueh, Tzu-Chien
%A Shekhar, Sudip
%A Balamurugan, Ganesh
%A O'Mahony, Frank
%A Roberts, Clark
%A Mooney, Randy
%A Casper, Bryan
%D 2013
%J IEEE J. Solid State Circuits
%K dblp
%N 12
%P 3229-3242
%T A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS.
%U http://dblp.uni-trier.de/db/journals/jssc/jssc48.html#MansuriJKHSBORMC13
%V 48
@article{journals/jssc/MansuriJKHSBORMC13,
added-at = {2020-08-30T00:00:00.000+0200},
author = {Mansuri, Mozhgan and Jaussi, James E. and Kennedy, Joseph T. and Hsueh, Tzu-Chien and Shekhar, Sudip and Balamurugan, Ganesh and O'Mahony, Frank and Roberts, Clark and Mooney, Randy and Casper, Bryan},
biburl = {https://www.bibsonomy.org/bibtex/291d9f891bf17378b4dde0f31ca9feedd/dblp},
ee = {https://doi.org/10.1109/JSSC.2013.2279052},
interhash = {c0ac6ad66945bf29e5078f5efffd469f},
intrahash = {91d9f891bf17378b4dde0f31ca9feedd},
journal = {IEEE J. Solid State Circuits},
keywords = {dblp},
number = 12,
pages = {3229-3242},
timestamp = {2020-08-31T11:44:06.000+0200},
title = {A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS.},
url = {http://dblp.uni-trier.de/db/journals/jssc/jssc48.html#MansuriJKHSBORMC13},
volume = 48,
year = 2013
}