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Disambiguation of "Roberts, Clark"

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A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS.

, , , , , , , , , and . IEEE J. Solid State Circuits, 48 (12): 3229-3242 (2013)

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Claudia Roberts

Yvonne Roberts

Adam Roberts

Rolf Roberts

Richard Roberts

 

Other publications of authors with the same name

A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 49 (12): 3079-3090 (2014)A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 48 (12): 3229-3242 (2013)26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS., , , , , , , , , and 6 other author(s). ISSCC, page 440-441. IEEE, (2014)A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS., , , , , , , , , and . ISSCC, page 402-403. IEEE, (2013)An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 43 (1): 29-41 (2008)26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS., , , , , , , , , and 3 other author(s). ISSCC, page 444-445. IEEE, (2014)A 47 , ˟, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 45 (12): 2828-2837 (2010)A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS., , , , , , and . VLSIC, page 346-. IEEE, (2015)Understanding Interaction Models: Improving Empirical Analyses, , and . Political Analysis, 14 (1): 63--82 (2006)