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Design considerations for low-power receiver front-end in high-speed data links., , , , and . CICC, page 1-8. IEEE, (2013)Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver., , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (8): 1818-1829 (2009)A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 58 (1): 8-18 (2023)A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 57 (1): 6-20 (2022)F6: Energy-efficient I/O design for next-generation systems., , , , , and . ISSCC, page 520-521. IEEE, (2014)10.5 A 5.9pJ/b 10Gb/s serial link with unequalized MM-CDR in 14nm tri-gate CMOS., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS., , , , and . VLSIC, page 1-2. IEEE, (2014)Session 6 overview: Ultra-high-speed wireline., , and . ISSCC, page 108-109. IEEE, (2017)A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS., , , , , , , , , and . ISSCC, page 402-403. IEEE, (2013)F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data., , , , , and . ISSCC, page 1-2. IEEE, (2015)