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Disambiguation of "Shekhar, Sudip"

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A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS.

, , , , , , , , , and . IEEE J. Solid State Circuits, 48 (12): 3229-3242 (2013)

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Sudip Roy

Sudip Kundu

Shekhar Priyadarshi

Sumit Shekhar

Hemabh Shekhar

 

Other publications of authors with the same name

Analog interference cancellation for full-duplex broadband power line communications., , and . ISPLC, page 1-6. IEEE, (2017)U-shaped slow-wave transmission lines in 0.18μm CMOS., , , , , and . ISCAS, page 1296-1299. IEEE, (2010)A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 48 (12): 3229-3242 (2013)A Type-I Sub-Sampling PLL With a 100×100 µm2 Footprint and -255-dB FOM., , and . IEEE J. Solid State Circuits, 53 (12): 3553-3564 (2018)Wideband CMOS Amplifier Design: Time-Domain Considerations., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (7): 1781-1793 (2008)A Compact, Voltage-Mode Type-I PLL With Gain-Boosted Saturated PFD and Synchronous Peak Tracking Loop Filter., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (1): 43-53 (2019)A capacitor cross-coupled common-gate low-noise amplifier., , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 52-II (12): 875-879 (2005)A Dual-Polarization Silicon-Photonic Coherent Transmitter Supporting 552 Gb/s/wavelength., , , , , and . IEEE J. Solid State Circuits, 55 (9): 2597-2608 (2020)A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 49 (12): 3079-3090 (2014)Session 2 - Wireline techniques for advanced modulation schemes., and . CICC, page 1. IEEE, (2017)